The subject invention relates to an analog to digital converter, computing all the bits in parallel and simultaneously without using any decoding logic.
The object of the subject application is to develop a system to be applied on different kinds of implementations offering different degrees of tradeoff between speed and hardware requirement.
Signals in the real world are real-valued, or analog in nature, as the output of a pressure or temperature sensor, the amplitude of a speech signal, etc. For example, the output voltage of a microphone may be 2 millivolts (mV) in response to a certain acoustic signal. Suppose that the output of the microphone ranges from a minimum of 0 mV to a maximum of 8 mV. The output of the microphone under consideration may typically be processed by some form of signal processing system.
Most processing equipment today are digital in nature, and they work with signals which are binary valued. In a digital or binary representation, a signal is represented by a word, which is composed of a finite number of bits.
The number of bits is termed as the word length, henceforth denoted by N. Since each bit in the word is either a 0 or a 1, the number of possible combinations is finite. The maximum number of possible binary numbers with N bits is equal to 2N. Since an infinite number of real values exist in a given analog range, the binary or digital representation is necessarily an approximate one.
If the output of the microphone can be represented by 3 bits, these bits are denoted by V1, V2 and V3. The number represented by the 3 bits (in millivolts) is given by V1+2V2+4V3. In general, with N bits, the digital representation is equal to       ∑          i      =      1        N    ⁢            2              i        -        1              ·          V      i      
where the significance of VN is the highest (it is weighted by 2Nxe2x88x921; this bit is termed as the Most Significant Bit (MSB). Conversely, V1 is termed as the Least Significant Bit (LSB).
The problem of analog-to-digital conversion is that of finding an N-bit binary word which best approximates a given analog value x, where N is an integer. An Analog to Digital Converter (ADC) for N bits has N output bits labeled V1 to VN, where each Vi, (i=1,2, . . . N) is either 0 or 1. Given an analog input whose value is denoted by a number x, the ADC is required to determine the values of V1 to VN such that the error   "LeftBracketingBar"      x    -                  ∑                  i          =          1                N            ⁢                        2                      i            -            1                          ·                  V          i                      "RightBracketingBar"
is minimized. If N is chosen to be 3, then the following table gives the outputs of a 3-bit ADC for different values of x. The values of x are assumed to lie within the range 0 to 8.
The existing methods of ADC as known conventionally include flash converters, dual-slope, ramp, sigma-delta, successive approximation, etc.
Presently, flash converters are the only known way of obtaining all the output bits in parallel. A N-bit flash converter requires of the order of 2N comparators. Let the input signal range from 0 to R. The range from 0 to R is divided into 2N levels. These comparators each output a 1 or 0 depending on whether the analog input x exceeds or is below the corresponding level. Decoding logic uses these 2N variables to generate the N output bits. The decoding logic is made up of gates. Practical considerations limit the number of inputs (fan-in) and fan-out of each gate. As a result, the delay due to decoding logic increases as O(N log2 N) or faster. These considerations limit the word length of a flash converter.
Since all the bits of a flash converter are obtained simultaneously, the time required to generate the output bits once the analog input has been presented is small.
In the case of a flash converter, the hardware grows exponentially with the number of bits; the number of comparators required for a N-bit converter is 2N and additional decoding logic is required.
Improved systems based on the flash converter use fewer comparators, where the number of comparators required can be written as 2KN, where K is a fraction between 0 and 1. In other words, the rate at which hardware requirements increase still remains an exponential function of N.
Other conventional approaches such as dual-slope and successive approximation methods require considerably less hardware. However, in these methods, the bits cannot be computed in parallel. As a result, the time taken to generate the binary approximation, which is termed as the conversion time, is much higher than for a flash Analog to Digital Converter.
The conversion time is closely related to the sampling rate that can be handled by the Analog to Digital Converter. This is the rate at which input samples can be accepted. Obviously, the next sample cannot be taken up by the ADC until the previous one has been converted.
In an other conventional frequency domain approach called sigma-delta conversion, the input signal is sampled at a high rate to achieve an analog to digital conversion. The scheme requires the extensive use of filters and additional hardware. An additional drawback is the need for the circuitry to work at a high speed, typically much higher than the sampling rate. This also creates hurdles with regard to hardware or circuit realization of such methods.
One approach to reducing the circuitry is known as a folding/interpolating type converter. As prior art of such a folding-interpolating ADC (FADC), there is, for example, that which is disclosed as U.S. Pat. No. 6,236,348 B1. In a folding/interpolating ADC, the input analog signal is converted into a set of n1 higher order bits and n2 lower order bits, where n1+n2=N. The idea in such a converter is to divide the range of the signal into segments. The higher order bits are obtained by determining the segment in which the value of a given input sample lies, while the n2 lower order bits are obtained by using 2n2 comparators and a suitable encoder.
Mandl, in patent U.S. Pat. No. 5,659,315, teaches us a method of accomplishing oversampled sigma-delta analog to digital conversion. The sampled analog signal is first converted using a ADC with a lower resolution. The conversion error is determined by obtaining the difference between the value of the digital word and the input sample. The error is fed to an integrator and again converted by using the ADC with a smaller resolution. In this manner, in succcessive steps, the quantization error reduces. In the limit, the smaller resolution ADC can be thought of as a one-bit ADC, which is no more than a comparator. Such a comparator compares a given input with a reference signal and outputs a xe2x80x9c1xe2x80x9d if the input exceeds the reference, and outputs a xe2x80x9c0xe2x80x9d if the input is less than the reference signal.
A variety of designs based on delta modulation have also been reported. Bader, in patent U.S. Pat. No. 4,291,300, teaches us a method of converting a time-varying (AC) signal which is superimposed on a larger, fixed (DC) component. It is concerned with tracking the time-varying part of the signal and its conversion, which is accomplished by means of a capacitive storage and by incremental variation of a reference signal. The variation of the reference signal is achieved by a series of clock pulses.
Another approach known as an Algorithmic ADC or cyclic ADC employs a very different approach. Kerth, in patent U.S. Pat. No. 5,644,308, discloses a design of an Algorithmic ADC. In an Algorithmic ADC, the conversion is carried out in a sequential manner, by employing the conventional restoring numerical division principle. The input signal sample is multiplied by two and the product is then compared with a reference. If the product exceeds the reference, then the output bit is set to xe2x80x9c1xe2x80x9d and the reference is subtracted from the product. Otherwise, the output bit is set to xe2x80x9c0xe2x80x9d and no subtraction is carried out. The remaining part of the product is treated as the signal for computing the next bit. In this manner, the desired number of bits are generated. Algorithmic converters suffer from differential and integral non-linearities, and errors in the gain of the conversion loop. Redundant signed digit (RSD) procedures have been used to overcome such difficulties. A related approach, which is outlined in U.S. Pat. No. 5,644,308 converts the redundant digital code to a digital output signal by computing a polynomial of a radix, where the redundant digital code specifies the co-efficient of the polynomial. This extends the analog input conversion range and reduces errors due to non-linearities.
In order to overcome the drawbacks associated with the existing methods of analog to digital conversion, the subject application has been devised, where all the bits can be computed in parallel or sequentially without using any decoding logic.
The subject system relates to the computation of all the output bits in parallel or sequentially, where the input x lies between 0 and R. The most significant bit (MSB), i.e VMSB is given by
VMSB=1 if xxe2x89xa7R/2
VMSB=0 if x less than R/2
Furthermore,
VMSB-1=1 if R/4 less than x less than R/2 OR if 3R/4 less than x less than R
VMSB-1=0 if 0 less than x less than R/4 OR if R/2 less than x less than 3R/4
The (MSB-i)-th bit denoted by VMSB-i can be computed by using the following formula VMSB-i=P[x/(R/2i)] where i ranges from 0 (corresponding to the MSB) to Nxe2x88x921 (corresponding to the LSB), where P(z) is a periodic pulse-shaped function of its argument z, having period equal to 1, the value of P(z) being 0 for z being less than 0.5 and 1 for values between 0.5 and 1.
In an another embodiment, the same formula may be written as VMSB-i=Sign [xe2x88x92sin(xcfx80x/(R/2i+1)], where Sign(z) is 1 if the argument z is positive and is 0 otherwise.
The present invention relates to an analog to digital converter computing all the bits in parallel or sequentially without using any decoding means having an analog input and a digital output, comprising
a means for sampling the analog input signal and holding the sample values;
a set of N functional blocks, each comprising a combination of non-linear gain blocks realizing periodic functions xe2x88x92sin [xcfx80x/(R/2i+1)], with i ranging from 0, corresponding to the MSB, to (Nxe2x88x921), corresponding to the LSB, the input to all the N functional blocks being the sampled analog value x, the output of each block feeding a Sign( ) block computing the sign of its input wherein the output of a Sign( ) block is zero if the input is non-positive and one otherwise, the outputs of the Sign( ) blocks representing the output digital word.
According to the present invention, analog to digital converter computing all the bits in parallel or sequentially without using any decoding means having an analog input and a digital output, wherein the digital output is a binary word comprised of the bits which are computed using the formula
VMSB-i=P[x/(R/2i)], i=0, 1, 2, . . . Nxe2x88x921
where VMSB denotes the Most Significant Bit, x is the analog input whose magnitude ranges from 0 to R, N is the number of bits in the output digital word, and P is a square wave form with period equal to 1.
The present invention also relates to an analog to digital converter computing all the bits sequentially without using any decoding means having an analog input and a digital output, comprising
means for sampling the analog input signal and holding the sample values;
counter block initialized having the initial counter value at 1 counting from 1 to N
multiplexer receiving the sample values from sample and holding means, wherein when the counter value is equal to 1, the multiplexer passes the input on line 1 to its output and the multiplexer passes the input on Line 2, to its output, when the counter value is any number other than 1 and the output from multiplexer is fed to a functional block as well as to a delay block (circuit);
delay mechanism connected to the output of multiplexer to delay the signal passed by multiplexer before being doubled;
doubler connected to the delay circuit and multiplexer, doubling the delayed signal to feed the doubled output signal to the multiplexer, wherein the multiplexer passes one of its inputs to the functional block depending upon the counter value;
functional block comprising a combination of non-linear gain blocks realizing formula of VMSB.
In another embodiment of the subject invention all the bits may be computed in parallel or sequentially without using any decoding means having an analog input and a digital output, comprising a means for sampling the analog input signal and holding the sample values, a start-of-conversion block, a set of N modules for determining each of the N bits of the digital word output, where N denotes the word length, each module consisting of a Ramp wavefrom generator, a Pulse Generator, a comparator, and a latch, wherein
the said sample and holding (S/H) block samples the analog input signal, holds the sample values and receives a trigger signal from the start of conversion block
the said start of conversion block holds the sample at the S/H block, and resets the outputs of the ramp generator, pulse generator and latch to zero.
In each module,
the Pulse Generator generates a square waveform P(t) with a constant time period T, where T denotes the conversion time, which is fixed depending on the application and the speed at which the converter is required to be operated. The pulse waveform is zero for time 0 to (T/2) and is equal to 1 for time (T/2) to T; then again zero for the next half period and so on.
The Ramp waveform generator generates an output given by kit, where ki is the slope of the ramp and t denotes time measured from the arrival of the Start of Conversion (SOC) pulse, and where ki is given by [R/(T*2i)] for the (MSB-i)-th bit or module, and where R denotes the range of the input signal x, i.e. x ranges from 0 to R
the Comparator generates the end-of-conversion signal when the sampled value and output of the Ramp generator are equal, and feeds a trigger signal to the latch to store and hold the value of the pulse generator when the said condition is true.
The Latch receives and stores the output of the pulse generator when the trigger output from the comparator is at its rising edge, signaling the end, of conversion of the input signal from analog to digital.
The said analog to digital converter comprises a plurality of circuits arranged in parallel for different bits from the most significant bit to least significant bit.
In another embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be supplied by a single ramp generator, wherein the input signal to the (MSB-i)th circuit is the analog sample x passed through a multiplier which multiplies it by a factor of 2i, i.e. the input to the (MSB-i)th circuit is equal to (x*2i), and output of the ramp generator is given by (R/T)t, where t denotes time measured from the arrival of the Start of Conversion (SOC) pulse and T denotes the conversion time.
In another embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be supplied by a single ramp generator and a single pulse generator, wherein the pulse waveform is a square wave with time period T; the input signal to the (MSB-i)th circuit is the analog sample x passed through a multiplier which multiplies it by a factor of 2i, i.e. the input to the (MSB-i)th circuit is equal to (x*2i), and output of the ramp generator is given by (R/T)t, where t denotes time measured from the arrival of the Start of Conversion (SOC) pulse and T denotes the conversion time.
In another embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be supplied by a single ramp generator and a single pulse generator, wherein the pulse waveform is a square wave with time period T; modules being arranged from the one computing the MSB to the one computing the LSB, each module but the last being equipped with a doubler; the input signal to each module being obtained by multiplying the input signal to the previous module by a factor of 2 with the use of doubler, with the MSB module receiving the analog sample x as input. No other multipliers are required in this case and the output of the ramp generator is given by (R/T)t, where t denotes time measured from the arrival of the Start of Conversion (SOC) pulse and T denotes the conversion time.
In another embodiment of the subject application, all the circuits generating various bits from the most significant bit to least significant bit may be supplied by a single ramp generator and a single pulse generator, wherein the pulse waveform is a square wave with time period T; modules being arranged from the one computing the LSB to the one computing the MSB, each module but the last being equipped with a halver or divide-by-two unit, the input signal to each module being obtained by dividing the input signal to the previous module by a factor of 2 with the use of halver, with the LSB module receiving the analog sample x as input. No other multipliers are required in this case and the output of the ramp generator is given by [R/(2Nxe2x88x921*T)]t, where t denotes time measured from the arrival of the Start of Conversion (SOC) pulse and T denotes the conversion time.
The subject application may better be understood with reference to the accompanying drawings and various embodiments involved therein. However, the same are for illustrative purposes only and should not be construed to restrict the scope of the invention.